In the paper Micro-coding the DDP-516 Computer a program to "scan" the instructions in Generic Group A is described. I've re-written this program in order to better understand the details of the instruction decoding.
- scan.asm
- Assembler source code
- scan.lst
- Assembler listing (HTML)
- scan.ptp
- Self-loading system tape (start '1000)
Scan results
- scan.res
- Plain ASCII. 930816 bytes
- scan.res.gz
- GNU zip. 20388 bytes
- scan.res.bz2
- bzip2 7099 bytes
Instruction decoding
The purpose of the scan program was to understand the instruction coding for this group of instructions. Micro-coding the DDP-516 Computer describes this, but the description is incomplete. Most of the remaining details were discovered by Bob Supnik and are detailed in one of his papers; Decoding the H316/H516 'Generic A' Instructions (cached). The text that follows is largely his.
A group A generic executes in 3 or 6 phases. A 'normal' instruction takes 3 phases:
| tlate | t2 extended into t3 |
| t3 | t3 |
| t4 | t4 |
A '1.5 cycle' instruction takes 6 phases:
| tlate | t2 extended into t3 |
| t3 | t3 |
| t2 | "special" t2 |
| tlate | t2 extended into t3 |
| t3 | t3 |
| t4 | t4 |
The key signals, by phase, are the following:
| tlate | EASBM | enable 0 to sum leg 2 (else 177777) | (m[9] || m[11] || azzzz) |
| JAMKN | jam carry network to 0 (force XOR) | ((m[12] || m[16]) && (!azzzz)) | |
| EASTL | enable A to sum leg 1 (else 0) | (JAMKN) || (EASBM) | |
| EIKI7 | force carry into adder | (m[15] && (c || (!m[13])) && (!JAMKN)) | |
| t3 | CLDTR | set D to 177777 (always) | |
| ESDTS | enable adder sum to D (always) | ||
| SETAZ | enable repeat cycle = set azzzz | (m[8] && m[15] && (!azzzz)) | |
| if not azzzz | |||
| t4 | CLATR | clear A register | (m[11] || m[15] || m[16]) |
| CLA1R | clear A1 register | (m[10] || m[14]) | |
| EDAHS | enable D high to A high register | ((m[11] && m[14]) || m[15] || m[16]) | |
| EDALS | enable D low to A low register | ((m[11] && m[13]) || m[15] || m[16]) | |
| ETAHS | enable D transposed to A high register | (m[9] && m[11] | |
| ETALS | enable D transposed to A low register | (m[9] && m[11]) | |
| GCBIT- | Clear C and OR overflow into C | (m[9] && (!m[11])) | |
| CBITE- | Set C bit | (m[8] && m[9]) | |
| CBITG- | OR D1 into C | (m[10] && m[12]) | |
| if azzzz | |||
| t2 | CLATR | clear A register (on due to azzzz) | |
| EDAHS | enable D high to A high register (on due to azzzz) | ||
| EDALS | enable D low to A low register (on due to azzzz) | ||
| tlate, t3, t4 as above | |||
For a "C++" program that models this see Proc::generic_group_A(unsigned short instr) in "proc.cc" of the emulator.
CMA/ACA Instructions
Micro-coding the DDP-516 Computer gives a summary of instructions. One is a combined CMA and ACA instruction (complement A and add carry to A). This instruction exists, but some of the encodings given cause a slightly different behaviour and set the C bit incorrectly:
* CMA/ACA
*********
140413 140417
* CMA/ACA - OR D1 into C
*********
140432 140433 140436 140437 140513 140517 140532 140533
140536 140537