F.I.G. Forth

* FIG FORTH FOR SERIES-16 MACHINES PAGE 35

1414 * HARDWARE UNSIGNED MULTIPLY 1415 * ONLY HAVE SIGNED MULTIPLY INSTRUCTION SO THIS CODE WORKS 1416 * BY BREAKING EACH 16-BIT UNSIGNED NUMBER INTO TWO FIELDS; 1417 * THE LOWER 15 BITS, WHICH (BEING A VALID SIGNED NUMBER) CAN 1418 * BE MULTIPLIED, AND THE TOP BIT, WHICH HAS SIGNIFICANCE 1419 * 2^15. SO WE HAVE: 1420 * (P1*2^15+P[2-16]) * (Q1*2^15+Q[2-16]) WHICH EQUALS... 1421 * P1.Q1*2^30 + P1*2^15*Q[2-16] + Q1*2^15*P[2-16] + P[2-16]*Q[2-16] 1422 01120 1 02 00001 LDA 1,1 ALL OF P 1423 01121 140100 SSP 1424 01122 0 04 00104 STA T1 BITS 2-16 OF P 1425 01123 000201 IAB 1426 01124 1 02 00002 LDA 2,1 ALL OF Q 1427 01125 140100 SSP 1428 01126 0 04 00105 STA T2 BITS 2-16 OF Q 1429 01127 0 16 00104 MPY T1 P[2-16]*Q[2-16] 1430 01130 0 04 00106 STA T3 SAVE UPPER BITS 1431 01131 000201 IAB GET LOWER 15 BITS (B1=0) 1432 01132 0 04 00107 STA T4 SAVE 1433 01133 140040 CRA CLEAR B REGISTER 1434 01134 000201 IAB 1435 * 1436 01135 1 02 00001 LDA 1,1 CHECK TOP BITS 1437 01136 101400 SMI 1438 01137 0 01 01164 JMP UST5 1439 01140 1 02 00002 LDA 2,1 1440 01141 101400 SMI 1441 01142 0 01 01161 JMP UST4 1442 * 1443 * BOTH TOP BITS SET 1444 01143 0 02 00106 LDA T3 UPPER BITS OF P[2-16]*Q[2-16] 1445 01144 0 06 00104 ADD T1 2^15*P[2-16] (2^15 FREE, SINCE 15-BITS IN B) 1446 * CAN'T OVERFLOW TO THIS POINTS SINCE BOTH 1447 * INPUTS TO PREVIOUS ADD WERE 15-BITS, BUT NOW HAVE 1448 * A 16-BIT VALUE AND ADDING A THIRD 15-BIT VALUE MAY 1449 * OVERFLOW 1450 01145 100400 SPL 1451 01146 0 01 01152 JMP UST2 1452 * TOP BIT CLEAR - CANNOT OVERFLOW 1453 01147 0 06 00105 ADD T2 2^15*Q[2-16] 1454 01150 0400 77 UST1 LRL 1 LS BIT OF A SHIFTS INTO B1, A1=0 1455 01151 0 01 01157 JMP UST3 1456 * TOP BIT WAS SET 1457 01152 0 06 00105 UST2 ADD T2 2^15*Q[2-16] 1458 01153 100400 SPL 1459 01154 0 01 01150 JMP UST1 IT STILL IS - NO OVERFLOW 1460 01155 0400 77 LRL 1 1461 01156 140500 SSM SET A1, DUE TO CARRY FROM ADD 1462 01157 0 06 00717 UST3 ADD ='040000 2^30 1463 01160 0 01 01174 JMP UST8