These are true schematics, rather than scanned images from a manual. In addition to giving a much smaller and cleaner file than scanned images, it is possible to produce a netlist of the H316 digital hardware which can then be simulated, as described here. In the process of debugging the netlist and getting the processor to run properly in simulation I've discovered a fairly long list of inaccuracies and mistakes in the published schematics, these are noted in the table below.
If you just want to download the schematics to study then you can simply download a ".pdf" file. The links on the first line of the table below will download a book containing all of the available sheets of schematics. Alternatively the schematics themselves can be downloaded using the links on this page.
The principal source for these schematics is:
H316 CENTRAL PROCESSOR, Instructions and
Doc. No. 70130072174G, M-493, February 1970.
|Title||LBD No.||Notes and Corrections|
|316 M.F. PAC COMP/ALLOC||100|
|COLUMN No.1||0.101||0.101||Missing gate D01FF+F added at h12,
located on A12 375 48.
Missing gate M01FF+F added at p10, located on A12 375 44.
nand4 D01EV+ at g9, corrected to nand5 with N02PA- as extra input.
|COLUMN No.2||0.102||0.102||Missing gate E01FF-F at p4, located on A12 375 18.|
|COLUMN No.5||0.105||0.105||Input to gate D05EU+ at g10, S06PA- corrected to S06CA-.|
|COLUMN No.9||0.109||0.109||M09FF- at m9, input CLMTR-D corrected to
Y09EP- at m10, input EPYTS+B corrected to EPYTS+.
B09SD- at g1, input SDBRS+B corrected to SDBRS.
|COLUMN No.10||0.110||0.110||B10SD- at g1, input B10SD- SDBRS+B
corrected to SDBRS.
Gate at d6, label O06PA+ corrected to O10PA+.
|COLUMN No.11||0.111||0.111||Gate at p1, delted since same gate A13D1
also drawn at p4.
SR11D- at b3, input A10FF+D corrected to A10FF+.
EA11D- at b4, input A11FF+D corrected to A11FF+.
EX11D- at b5, input X11FF+D corrected to X11FF+.
EM11D- at b9, input M11FF-O corrected to M11FF-.
EN11D- at b10, input M11FF+O corrected to M11FF+.
EP11D- at b11, input P11FF-O corrected to P11FF-.
EY11D- at b12, input Y11FF-O corrected to Y11FF-.
Y11EP- at m10, input EPYTS+B corrected to EPYTS+.
|COLUMN No.12||0.112||0.112||JAMKN-D at d9, added edge connector
Note: A12EE- at, k4 output shown on B12, but also B12 shown on LBD 0.110 k4.
A12SR- at k6 input D11FF- corrected to D11FF+.
Missing gate M12FF-A added at m7, located on A04 370 75.
B12SD- at g1, input SDBRS+B corrected to SDBRS.
|COLUMN No.14||0.114||0.114||A14FF+ at m4, added missing location
A14FF- at m5, added missing location 54.
B14SD- at g1, input SDBRS+B corrected to SDBRS.
|COLUMN No.15||0.115||0.115||N15PA- at d9 input JAMKN- corrected to
A15ET- at g3 PAC location A06 correctd to A08.
|COLUMN No.16||0.116||0.116||EN16D- at b9, corrected to EM16D-.
EP16D- at b11, position B3 corrected to 83.
Y16FF- at p11, input E0Y16- corrected to EOY16- (digit zero to letter 'O').
|CARRY NETWORK||0.117||0.117||S10CA- at h7, input O09PA+ corrected to S10CC+.|
|TLG & CLOCK||0.118||0.118|
|PHASE REGISTER||0.119||0.119||Missing gate EOINS-C added at g1, located on A09 372 D5.|
|F REG AND OP DECODE||0.120||0.120|
|CONTROL LOGIC A||0.122||0.122||S26OR- at a11, input SC12F- corrected to SC12F+.|
|CONTROL LOGIC B||0.123||0.123||EDBTP- at m2, input MCSET+B corrected to
MDA2C- at g10, input MPYOP- corrected to MPYOP+F.
|CONTROL LOGIC C||0.124||0.124||Note: There are two instance called
CBITF-, at p1 and e7, to disambiguate, renamed the one at
e7 to CB1TF- (digit one).
DPMOC- at b8, input MCSET+B corrected to MCSET+.
B01AC+ at e10, input MCSET+B corrected to MCSET+.
MADAC- at h6, input MCSET+B corrected to MCSET+.
MADSR- at l7, input MCSET+B corrected to MCSET+.
Missing gate MADFF+F added at h10, located on A12 370 81.
Missing gate SCZR0+G added at b12, located on A11 401 27.
CLCBP- at l1, input MCRST+A corrected to MCRST+.
B01AC+ at e10, input SCZR0+ from  corrected to SCZR0+G local to this sheet (at b12).
|CONTROL LOGIC D/E||0.125||0.125||A16FF+G at a8, input A16FF+ corrected to
ESDTB- at c5, input TL3FF+ comes from sheet  corrected to .
DRFLI- at c11, input MCSET+B corrected to MCSET+A.
ESTDP- at k4, input MCSET+B corrected to MCSET+A.
EICTS- at k9, input MCSET+B corrected to MCSET+A.
EIDTS- at m6, input MCSET+B corrected to MCSET+A.
AZZZZ+ at e7, input MCSET+B corrected to MCSET+A, and moved to clock input of gate.
ECETP- at k3, input MCSET+A edge connector location B32 corrected to B22.
EIHCL- at h10, input AIQA2+ corrected to A1QA2+ (letter 'I' to digit one).
SETZB- at c12, input DGONE-D corrected to DGONE-.
M2910+ at a1, input M02FF-C should be M02FF-A.
M2910+ at a1, input M09FF-C should be M09FF-A.
(Note however, that M10FF-C is correctly shown.)
|CONTROL LOGIC H||0.126||0.126||MCSET-C at a1, input MCSET+B corrected
RRCXX- at m8, input DMCWR- from  corrected to .
Gate at g7, label EM0OR- corrected to EMCOR-.
RRCXA- at m9, input BANKA+ from  corrected to .
|CONTROL LOGIC||0.127||0.127||Several confusions of digits zero and
one with letters 'O' and 'I':
EMSAM- at a9, input A0QM1- corrected to AOQMI-.
ENMSL- at g8, input A0QM1- corrected to AOQMI-.
ENSBL- at d8, input A0QM1+ corrected to AOQMI+.
ENSBM- at d9, input B15FF+F corrected to B15FF+.
ENSBM- at d9, input B15FF+F corrected to B15FF+.
ENSBN- at d10, input B15FF+F corrected to B15FF+.
EASCM- at g1, input B16FF+F corrected to B16FF+.
EMSAN- at a11, input B16FF+F corrected to B16FF+.
ACERA- at d4, input ERAOP+B corrected to ERAOP+.
K17AM+ at a6, input SCZR0+G from  corrected to .
|CONTROL LOGIC MX||0.128||0.128||Note: IRSOP+C at a4, is also shown on
schematic 119 at a2.
Note: LSXOP+D at g9, is also shown on schematic 126 at a7.
Note: OPGSM- at d12, is also shown on schematic 122 at p10.
SRSTL- at g1, input B16FF+F corrected to B16FF+.
EXSTM- at k5, input LSXOP- from  corrected to LSXOP+D local to this sheet (at g9).
|CONTROL LOGIC PY||0.129||0.129||AZM11- at c9, input AZERO- corrected to
AZER0- (letter 'O' to digit zero).
Gate at f7, label EDPIA- corrected to EDPTA-.
OPGJS-A at j10, input M07FF+D corrected to M07FF+B.
SKSXX-A at g11, edge connector location A04 corrected to A09.
|CONTROL LOGIC PY||0.130||0.130||Note: On gates at a2 and a3, both M08FF+
and M08FF- shown on edge connector A32.
SDB2B+ at a9, position B2 correctd to 82.
SDB1B at a6, input SCZR0+F from  corrected to .
|LAMP DRIVER 1-8||0.132||0.132|
|LAMP DRIVER 9-16||0.133||0.133|
|CONTROL LOGIC I/O||0.134||0.134||CLPIL- at m6, input EQINS+ should be
SETFA- at a7, input IGO63+ should be IG063+ (letter 'O' to digit zero).
NAND2 at d6, ADB07-A, should be NAND1. Input TL1FF+ incorrect - delete.
|INTERRUPT ADDRESS ENCODING||0.135||0.135||Rename m6 (IBY16) as IYB16.
IADND- at m7, position D6 deleted (since AND gates, i.e. expansion diodes, don't have a location).
|CONTROL PANEL SWITCHES||0.141|
|CONSOLE AND I/O CONNECTIONS||0.142||0.142||A1AA18-15 SENS1+ sheet  corrected
A1CA18-23 M16FF- corrected to M16FF+.
A1CA17-16 MMT1F- corrected to MM11F-
|REAL TIME CLOCK||0.147||0.147|
|POWER SUPPLY & POWER DISTRIBUTION||0.148|
|TIMING & CONTROL||0.150||0.150|
|ASR 33/35 CONTROL||0.340||0.340||TYCFA+ at c6, input TYKIP+ corrected to
TYK1P+ (letter 'I' to digit one).
TSFTB- at g7, input TYKIP+ corrected to TYK1P+ (letter 'I' to digit one).
|BUFFER REGISTER ASR 33/35||0.341||0.341||PREST- (reset) and TYSFT+ (clock)
swapped to all shift register flops in upper row.
NAND2, TYOCP+, at a2 should be NAND1 with input TYOCP-.
NAND1, TYSET-, at b2 should be NAND2, second input is PREST-.
|ADDRESS & SKS ASR 33/35||0.342||0.342||RRLIN+W at e2, input RRLIN- added
missing edge connector location C11.
Gate at e8, label ADB10+W corrected to ADB10-W.
Gate at e10, label ODB08-W corrected to ADB08-W.
|MEMORY EXPANSION: MEMORY TIMING & CONTROL||0.000||0.000|
|MEMORY EXPANSION: ADDRESS GATING & DATA REGISTER BITS 1-5||0.001||0.001|
|MEMORY EXPANSION: DATA REGISTER BITS 6-14||0.002||0.002|
|MEMORY EXPANSION: DATA REGISTER BITS 15-16 & BANK SIGNALS||0.003||0.003|
|MEMORY EXPANSION: C.P. & MEMORY CONN.||0.004||0.004|
|MEMORY EXPANSION: PAC COMP/ALLOC 1X3||0.005|
|MEMORY EXPANSION/PARITY: ADDRESS & CONTROL||0.006||0.006|
|MEMORY EXPANSION/PARITY: MEMORY DATA IN/OUT||0.007||0.007|
|MEMORY EXPANSION/PARITY: C.P. CONNECTORS||0.008||0.008|
|H-316 SDMC PRIORITY NET||0.231||0.231|
|H-316 SDMC CYCLE & TLG||0.232||0.232||nand2, TBSET+, f11 corrected to
nand3, SETTA-, l10 corrected to SETTB-
|H-316 SDMC CONTROL||0.233||0.233|
|H-316 SDMC M-REG STORAGE||0.234||0.234|
|H-316 SDMC M-REG INPUT||0.235||0.235|
|H-316 SDMC ADDRESS REG.||0.236||0.236|
|H-316 SDMC COMPARATOR/IYB||0.237||0.237|
|H-316 SDMC CABLE & OUT BUS||0.238||0.238||DMC connector A1AA20 pin 19 should be
TL23F- (not TL23F+)
DMC connector A1AA20 pin 8 should be IOACY+ (not IOACY-)
nand2, IOACY-, at c1 corrected to IOACY+
|ML SECTOR DECODE||0.261||0.261||Correct nand2b b3 input 1 to pin 16 (not
Correct nand2b m5 to be TG335 (not TG336)
|ML BASE SECTOR RELOCATION||0.263||0.263|
|ML PROTECT DECODER||0.264||0.264|
|Z SEC REGISTER||0.268||0.268|
|MLO EXTERNAL I/O BUS INTERFACE||0.270||0.270|
|LOCKOUT MASK REGISTER #1||0.271||0.271|
|LOCKOUT MASK REGISTER #2||0.272||0.272|
|LOCKOUT MASK REGISTER #3||0.273||0.273|
|LOCKOUT MASK REGISTER #4||0.274||0.274|
|ML EXTERNAL CABLES||0.275||0.275|